Re: Guidelines for instruction set design?

<cyril.cressent@gmail.com> wrote in message news:09-05-020@comp.compilers...


> - 32-bits RISC, implemented in a FPGA
> - Big Endian
> - Multipurpose, though it has a MULAC module for signal processing
> - Word adressable
>
> - $R0..15: 32-bits general purpose registers.
>
> - $C0..15: 32-bits "Counter" registers.


(I always have trouble with special purpose registers (eg. Motorola 68K with
Data and Address registers). Things are much easier when all registers are
orthogonal.)


> They can be used to load a
> constant or an address and to do indirect memory addressing.


So you don't have direct memory addressing, but have to load the address
into $Cn first and access that indirectly?


I'm not familiar with how LCC works; why can't a single Load or Store
operation map into two or more of your instructions (load address then
indirect access)?


--
Bart

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