Re: Guidelines for instruction set design?

On May 5, 7:33 pm, George Neuner <gneun...@comcast.net> wrote:
> On Mon, 4 May 2009 02:57:34 -0700 (PDT), cyril.cress...@gmail.com
> wrote:
>
> >About my CPU architecture:
>
> >- 32-bits RISC, implemented in a FPGA
> >- Big Endian
> >- Multipurpose, though it has a MULAC module for signal processing
> >- Word adressable
> ...
> Except for those extra registers it looks a lot like a 68K
> architecture. ...
> I don't know whether there are any open source PDP compilers lying
> about (anybody?),


As it happens I did a (mostly complete) lcc back-end for PDP-11.
http://telegraphics.com.au/svn/lcc_pdp11/trunk/
Discussion @ http://telegraphics.com.au/sw/info/lcc-pdp11.html


There are a number of gotchas in writing machine descriptions for lcc
- which is aimed at reasonably modern CPUs. For example, it is rather
tricky to achieve support for a 32 bit type on PDP-11, which is why my
back-end hasn't done that. :)


Word addressable architectures can also be tricky in lcc. Some byte
operations will simplify the machine description, I think. 68K is one
of its targets.


Source to some freely available 68K compilers is archived here:
http://telegraphics.com.au/svn/smallcnova/trunk/

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