Re: Guidelines for instruction set design?

On Mon, 4 May 2009 02:57:34 -0700 (PDT), cyril.cressent@gmail.com
wrote:


>About my CPU architecture:
>
>- 32-bits RISC, implemented in a FPGA
>- Big Endian
>- Multipurpose, though it has a MULAC module for signal processing
>- Word adressable
>
>- $R0..15: 32-bits general purpose registers.
>
>- $C0..15: 32-bits "Counter" registers. They can be used to load a
>constant or an address and to do indirect memory addressing. They also
>support post-inc/decrementation, if you append ++ or -- to the
>register name.
>
>- $CON: a register hardwired to 0xFFFFFFFF
>
>- $ACC: 70-bits accumulator register. It's the destination register
>for MULAC operations
>- $DIV: 48-bits special register holding the integer result of a div
>instruction
>- $MOD: 48-bits special register holding the modulus after a div
>instruction
>
>It uses a scratchpad memory, with data and instruction memory
>separated.
>
>Addressing modes:
>
>- immediate ; I can fetch a word in the scratchpad with it's direct
>address --> d(100)
>- indirect ; via $C register ---> d($C0)
>- $C register + offset ---> d($C0)+5


Why are the accumulator and div/mod result registers odd sizes?


Except for those extra registers it looks a lot like a 68K
architecture. You might want to look at how GCC handles data and
address registers in the 68K (or possibly just look into retargeting
GCC's 68K code generator to your design).




>It causes me problems mainly because it's not really load store based,
>like most other CPU.


General register load/store architectures really began with RISC.
8-bit and 16-bit chips were usually accumulator designs, and if you
look at older 32-bit (and above) processors like m68K, we32K, VAX,
etc. you'll see that many of them had memory->memory operations.




>- It's hard to allocate registers, for example for common
>subexpression, since I can directly use memory operands.


Does your FPGA have scratchpad RAM? If so, you might want to look at
using part of it as a memory mapped register set. See
http://en.wikipedia.org/wiki/Addressing_mode#Memory-mapped_registers
and read to the end of the article.


I don't know whether there are any open source PDP compilers lying
about (anybody?), but there are open source compilers for 65xx, 68xx
and Transputer that you can look at for inspiration. Ignore the focus
on variable length instructions and concentrate on how the compilers
use their "memory registers" for handling temporary values.


>- some memory operand are forced to some addressing modes.


That's the case with nearly all accumulator designs. There should
already be examples of handling that in LCC for the x86.


George

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