Re: Branch prediction hints in an ISA

VBDis <vbdis@aol.com> wrote :
....
> I also remember "delayed" jumps in some machine architecture. This means that
> one (or more?) instructions can be executed after a (conditional) jump
> instruction, while the processor can start to fetch instructions from the
> actual continuation address.
....
> [SPARC has delayed branch, the instruction after a branch is always executed
> to fill an execution pipeline slot. I don't know any new designs that do
> that, out of order execution makes that hack pretty unhelpful. -John]


MIPS has (had) a delay slot for branches and loads (and a few
weirdos); although normally that insn is executed before the branch
successor, the branch can optionally nullify if the branch is not
taken.


IME explicit pipelining, including delayed branches, is more common in
microarchitectures, which is usually an issue for chip/CPU makers
since they are the only microcode writers, although some machines have
allowed user-written microcode (my favorite was the LSI-11/2).


I agree OOO (and speculation) has pretty much obsoleted this.


--
- David.Thompson 1 now at worldnet.att.net

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