Re: Branch prediction hints in an ISA

  timgleason@my-deja.com schreibt:
>[Yes, it's been done many times. IA-64, for example, has it. I gather
>that static branch prediction is OK, but it's no substitute for dynamic
>branch prediction. -John]


Agreed, dynamic branch prediction is more reliable ;-)


I also remember "delayed" jumps in some machine architecture. This means that
one (or more?) instructions can be executed after a (conditional) jump
instruction, while the processor can start to fetch instructions from the
actual continuation address.


I'm not sure of the details, perhaps it was a machine where multiple
instructions could reside in a machine "word", and that a jump instruction
always executed after all the other instructions in the same word.


DoDi
[SPARC has delayed branch, the instruction after a branch is always executed
to fill an execution pipeline slot. I don't know any new designs that do
that, out of order execution makes that hack pretty unhelpful. -John]

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