Modeling the condition code register in register allocation

Hello everyone,


I am currently writing a small compiler as a hobby project. My
register allocator is basicly working but I have no idea how I could
model the condition code register (rflags) properly. AMD64 is my
current backend. My intermediate representation (SSA based) handles
comparisons and conditional jumps like this at the moment:


a = b + c
d = a > 10
IF d GOTO label1 ELSE GOTO label2
label2
...
label1
...


a, b, c are longs for instance and d is a bool. My allocator finds
something like this:
a -> %rax
b -> %rbx
c -> %rcx
d -> %dl (because d is a bool)


Somehow I can surely find code for this but this will be far from
optimal. I would like code like this:


addq ...
cmpq $10, %rax
jg label1
label2:
...
label1:
...


So %dl is actually not needed. Things get even worse when there is
something like this:


a = b + c
d = a > 10
e' = e + 1
IF d GOTO label1 ELSE GOTO label2
label2
...
label1
...


with
e -> %rsi
e' -> %rsi


The e' = e + 1 can be compiled to incq %rsi which does not touch the
rflags register. When there is e = e + 2 it could be tranlated to
addq $2, %rsi
or
inc %rsi
inc %rsi
or
the instruction is scheduled even before d = a > 10.


The first variant touches rflags, the second doesn't. As one can
easily see this will be tricky to model especially when the
intermediate representation should be as architecture independent as
possible.


Some ideas or related papers?


Cheers,
Roland Leissa

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