Re: Modeling the condition code register in register allocation

First of all: Thanks everyone for replying.


Most ideas mentioned so far have come to my mind, too. And all have
their drawbacks:


1. Just relying on peephole optimization has the disadvantage that a
register is being allocated which could have been used otherwise.


2. Completely modeling the CCR with the register allocator is surly a
more or less optimal way but properly constraining every instruction
which touches one of the condition codes would render this very
complicated: The allocator has to know how a IR-instruction is
translated to a AMD64 code sequence in advance. Furthermore almost
every instruction would be constrained. And since I do live range
splitting on every constrained instruction this will become a heavy
overkill.




This is what I will probably do:


I leave my allocator roughly like it is. I translate:
a = b > c
to
cmpq %rcx, %rbx
setgb %al


and
IF a THEN GOTO L1 ELSE GOTO L2
to
test %al, %al
jz L2
jmp L1


But:


If -- during register targeting -- a comparison is followed by a
branch which uses the comparison's result as only use I don't allocate
a register for this at all:
cmp %rcx, %rbx
jng L2
jmp L1


If the comparison's result is followed by a branch which uses the
result and the result has more uses I allocate a register and do this:
cmp %rcx, %rbx
setg %al
jng L2
jmp L1


Superfluous jmp instructions can be optimized away by a peephole
optimization.




I guess this variant should generate quite good code while still being
quite easy to implement.


---
Cheers,
Roland

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