Re: Software Pipelining

Neeraj Goel <mr.neeraj@gmail.com>
Tue, 2 Sep 2008 22:32:58 -0700 (PDT)

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Related articles
Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-26)
Re:Software Pipelining Jatin_Bhateja@mentor.com (Jatin Bhateja) (2008-08-28)
Re:Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-28)
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-08-29)
Re: Software Pipelining mr.neeraj@gmail.com (Neeraj Goel) (2008-09-02)
Re: Software Pipelining sidtouati@inria.fr (Touati Sid) (2008-09-08)
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Re: Software Pipelining johnhull2008@gmail.com (johnhull2008) (2008-09-11)
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16)
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16)
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-09-17)
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From: Neeraj Goel <mr.neeraj@gmail.com>
Newsgroups: comp.compilers
Date: Tue, 2 Sep 2008 22:32:58 -0700 (PDT)
Organization: Compilers Central
References: 08-08-072 08-08-086 08-08-092 08-08-098
Keywords: code, optimize
Posted-Date: 03 Sep 2008 05:20:19 EDT

Also, the overheads of modulo scheduling can make it worse.
Overheads include, more registers, prolog and epilog instructions.
As Tim said, only advantage is in hiding latencies such as memory
access
and floating point.


=Neeraj


On Aug 29, 5:42 pm, Pertti Kellomaki <pertti.kellom...@tut.fi> wrote:
> Tim Frink wrote:
> > My question was if also a significant performance increase for RISC
> > architectures with a restricted number of functional units can be
> > expected when software pipelining is applied.
>
> I'm not sure about significant increase, but it seems that even with
> a small number of FUs pipelining could be used to hide latency (e.g.
> memory access). But if FUs are already busy without software
> pipelining, then pipelining is not going to make them any busier.

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