Related articles |
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Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-26) |
Re:Software Pipelining Jatin_Bhateja@mentor.com (Jatin Bhateja) (2008-08-28) |
Re:Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-28) |
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-08-29) |
Re: Software Pipelining mr.neeraj@gmail.com (Neeraj Goel) (2008-09-02) |
Re: Software Pipelining sidtouati@inria.fr (Touati Sid) (2008-09-08) |
Re: Software Pipelining kamalpr@hp.com (kamal) (2008-09-10) |
Re: Software Pipelining johnhull2008@gmail.com (johnhull2008) (2008-09-11) |
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16) |
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16) |
[5 later articles] |
From: | Pertti Kellomaki <pertti.kellomaki@tut.fi> |
Newsgroups: | comp.compilers |
Date: | Fri, 29 Aug 2008 15:42:19 +0300 |
Organization: | Compilers Central |
References: | 08-08-072 08-08-086 08-08-092 |
Keywords: | optimize, architecture |
Posted-Date: | 29 Aug 2008 12:37:11 EDT |
Tim Frink wrote:
> My question was if also a significant performance increase for RISC
> architectures with a restricted number of functional units can be
> expected when software pipelining is applied.
I'm not sure about significant increase, but it seems that even with
a small number of FUs pipelining could be used to hide latency (e.g.
memory access). But if FUs are already busy without software
pipelining, then pipelining is not going to make them any busier.
--
Pertti
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