Related articles |
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Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-26) |
Re:Software Pipelining Jatin_Bhateja@mentor.com (Jatin Bhateja) (2008-08-28) |
Re:Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-28) |
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-08-29) |
Re: Software Pipelining mr.neeraj@gmail.com (Neeraj Goel) (2008-09-02) |
Re: Software Pipelining sidtouati@inria.fr (Touati Sid) (2008-09-08) |
Re: Software Pipelining kamalpr@hp.com (kamal) (2008-09-10) |
[8 later articles] |
From: | Tim Frink <plfriko@yahoo.de> |
Newsgroups: | comp.compilers |
Date: | 26 Aug 2008 14:57:06 GMT |
Organization: | Compilers Central |
Keywords: | optimize, architecture, question |
Posted-Date: | 26 Aug 2008 23:33:35 EDT |
Hi,
Software pipelining is a technique to reorder loops to achieve more
parallelism at the instruction level. I was wondering if this
optimization is mainly beneficial for processors that have multiple
functional units like VLIWs, or can significant performance
improvements be also achieved for RISC processors with a restricted
number of functional unis like just two 4-stage pipelines?
I was also wondering if software pipelining can benefit from profiling
information, i.e. can the knowledge about frequently executed paths be
exploited for a better pipelining? Do you know any successful
applications?
Regards,
Tim
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