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| [11 earlier articles] |
| Re: Green Compiler ? gah@ugcs.caltech.edu (glen herrmannsfeldt) (2012-12-28) |
| Re: Green Compiler ? anton@mips.complang.tuwien.ac.at (2012-12-28) |
| Re: Green Compiler ? gneuner2@comcast.net (George Neuner) (2012-12-28) |
| Re: Green Compiler ? z80eu@arcor.de (Peter Dassow) (2012-12-29) |
| Re: Green Compiler ? DrDiettrich1@aol.com (Hans-Peter Diettrich) (2012-12-30) |
| Re: Green Compiler ? mailbox@dmitry-kazakov.de (Dmitry A. Kazakov) (2012-12-30) |
| Re: Green Compiler ? gneuner2@comcast.net (George Neuner) (2012-12-31) |
| Re: Green Compiler ? jthorn@astro.indiana.edu (Jonathan Thornburg) (2013-01-02) |
| Re: Green Compiler ? gah@ugcs.caltech.edu (glen herrmannsfeldt) (2013-01-02) |
| Re: Green Compiler ? DrDiettrich1@aol.com (Hans-Peter Diettrich) (2013-01-02) |
| Re: Green Compiler ? gah@ugcs.caltech.edu (glen herrmannsfeldt) (2013-01-02) |
| Re: Green Compiler ? gah@ugcs.caltech.edu (glen herrmannsfeldt) (2013-01-02) |
| Re: Green Compiler ? numerist@aquaporin4.com (Charles Richmond) (2013-01-04) |
| From: | George Neuner <gneuner2@comcast.net> |
| Newsgroups: | comp.compilers |
| Date: | Mon, 31 Dec 2012 01:24:13 -0500 |
| Organization: | A noiseless patient Spider |
| References: | 12-12-010 12-12-012 12-12-022 12-12-028 12-12-034 12-12-037 |
| Keywords: | performance, architecture |
| Posted-Date: | 01 Jan 2013 20:54:04 EST |
On Sun, 30 Dec 2012 08:14:26 +0100, Hans-Peter Diettrich
<DrDiettrich1@aol.com> wrote:
>Peter Dassow schrieb:
>> On 28.12.2012 08:35, Hans-Peter Diettrich wrote:
>>>
>>> Please note that most CMOS processor power consumption results from
>>> switching (stray) capacities, and only a small percentage for leak
>>> currents. E.g. a register or gate consumes such power whenever a bit is
>>> changed, and almost nothing when it has reached an stable state.
Smaller transistors have more leakage.
>> So using extensively registers instead of "conventional" memory (e.g.
>> DDR-RAM, memory outside a CPU) will save energy (if equal functionality
>> is given) ?
>
>I don't see a relationship here, except that external memory is slow
>and [in x86] a couple of caches and address translations are involved
>in reading from RAM.
But associative cache and external memory accesses both are power
intensive.
>But registers are a very scarce resource, so that frequent loading from
>memory is hardly avoidable.
My opinions are colored by experience with DSPs, but I have long
thought that it would be helpful to have a few K-words of non-cache
scratchpad memory very close (1..2 cycles) to the CPU.
George
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