|Superscalars and instruction scheduling email@example.com (Pertti Kellomaki) (2008-11-13)|
|Re: Superscalars and instruction scheduling firstname.lastname@example.org (Ricardo Nabinger Sanchez) (2008-11-17)|
|Re: Superscalars and instruction scheduling SidTouati@inria.fr (Sid Touati) (2008-11-18)|
|Re: Superscalars and instruction scheduling email@example.com (Mayan Moudgill) (2009-02-28)|
|Re: Superscalars and instruction scheduling SidTouati@inria.fr (Touati Sid) (2009-03-04)|
|From:||Mayan Moudgill <firstname.lastname@example.org>|
|Date:||Sat, 28 Feb 2009 22:46:13 -0500|
|References:||08-11-053 08-11-077 08-11-084|
|Posted-Date:||02 Mar 2009 08:34:13 EST|
>>Maybe you're looking for papers on cycle-accurate simulation of
>>processors. If those are not useful, at least they will provide you
>>with pointers to (hopefully) what you really want.
> However, you should be aware that no simulator exists till now that has
> been validated by statistics. The simulation errors are unfortunately
> not neglectible.
Not exactly true: see "Validation of Turandot, a fast processor model
for microarchitecture exploration", IPCCC 1999.
The Turandot simulator was within 5% for the Power-4
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