|Superscalars and instruction scheduling email@example.com (Pertti Kellomaki) (2008-11-13)|
|Re: Superscalars and instruction scheduling firstname.lastname@example.org (Ricardo Nabinger Sanchez) (2008-11-17)|
|Re: Superscalars and instruction scheduling SidTouati@inria.fr (Sid Touati) (2008-11-18)|
|Re: Superscalars and instruction scheduling email@example.com (Mayan Moudgill) (2009-02-28)|
|Re: Superscalars and instruction scheduling SidTouati@inria.fr (Touati Sid) (2009-03-04)|
|From:||Sid Touati <SidTouati@inria.fr>|
|Date:||Tue, 18 Nov 2008 16:05:18 +0100|
|Posted-Date:||18 Nov 2008 19:11:55 EST|
Ricardo Nabinger Sanchez a icrit :
> Maybe you're looking for papers on cycle-accurate simulation of
> processors. If those are not useful, at least they will provide you
> with pointers to (hopefully) what you really want.
However, you should be aware that no simulator exists till now that has
been validated by statistics. The simulation errors are unfortunately
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