Superscalars and instruction scheduling

Pertti Kellomaki <pertti.kellomaki@tut.fi>
Thu, 13 Nov 2008 15:04:08 +0200

          From comp.compilers
Related articles
Superscalars and instruction scheduling pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-11-13)
Re: Superscalars and instruction scheduling rnsanchez@wait4.org (Ricardo Nabinger Sanchez) (2008-11-17)
Re: Superscalars and instruction scheduling SidTouati@inria.fr (Sid Touati) (2008-11-18)
Re: Superscalars and instruction scheduling mayan@bestweb.net (Mayan Moudgill) (2009-02-28)
Re: Superscalars and instruction scheduling SidTouati@inria.fr (Touati Sid) (2009-03-04)
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From: Pertti Kellomaki <pertti.kellomaki@tut.fi>
Newsgroups: comp.compilers
Date: Thu, 13 Nov 2008 15:04:08 +0200
Organization: Compilers Central
Keywords: optimize, architecture, question
Posted-Date: 13 Nov 2008 19:47:19 EST

One quite frequently hears the claim that while good instruction
scheduling is a must for VLIWs and similar architectures, it is
not needed for superscalars. However, a superscalar processor only
has a limited window into the program, which may limit the
opportunities for exploiting ILP.


Googling for "superscalar instruction scheduling performance" gives
hits to fairly old papers. Does anyone know how important (if at all)
instruction scheduling is for getting good performance out of modern
superscalar processors?
--
Pertti


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