Re: Pitfalls in interference graph ?

> Colouring hurts ILP extraction for both superscalar VLIW and EPIC
> processors. Even if the ILP is not exposed at the architectural level,
> compilers schedule operations to help the processor to extract it at
> execution time.


I can see how it would hurt ILP extraction if you do register
allocation before scheduling, but if you do it after scheduling I
don't see the problem. Perhaps you could explain the issue in a bit
more detail?


> If register allocation with coloring methods are used, the ILP of the
> generated code would not be easily extracted by the processor at
> execution time. Dynamic renaming is limited in practice (since the
> window od instructions is limited).


Dynamic renaming is certainly limited, but surely the instruction
window on any reasonable OOO processor is big enough to allow renaming
to take care of almost all false dependencies.

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