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| Related articles |
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| [5 earlier articles] |
| Re: Pitfalls in interference graph ? marcov@stack.nl (Marco van de Voort) (2007-10-01) |
| Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-01) |
| Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-01) |
| Re: Pitfalls in interference graph ? jeremy.wright@microfocus.com (Jeremy Wright) (2007-10-02) |
| Re: Pitfalls in interference graph ? shafitvm@gmail.com (shafi) (2007-10-15) |
| Re: Pitfalls in interference graph ? torbenm@app-6.diku.dk (2007-10-17) |
| Re: Pitfalls in interference graph ? SidTouati@inria.fr (ST) (2007-10-18) |
| Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-21) |
| Re: Pitfalls in interference graph ? Sid.Touati@uvsq.fr (Sid Touati) (2007-10-24) |
| Re: Pitfalls in interference graph ? parthaspanda22@gmail.com (2007-10-24) |
| From: | ST <SidTouati@inria.fr> |
| Newsgroups: | comp.compilers |
| Date: | Thu, 18 Oct 2007 12:52:58 +0200 |
| Organization: | I.N.R.I.A Rocquencourt |
| References: | 07-09-10407-10-003 07-10-021 |
| Keywords: | registers, optimize |
| Posted-Date: | 18 Oct 2007 09:50:57 EDT |
Rayiner Hashem a icrit :
> Huh? Where is the dependence on sequential processing in graph
> coloring allocation? Moreover, only a few non mainstream archs expose
> non sequential semantics at the ISA level anyway.
>
Colouring hurts ILP extraction for both superscalar VLIW and EPIC
processors. Even if the ILP is not exposed at the architectural level,
compilers schedule operations to help the processor to extract it at
execution time.
If register allocation with coloring methods are used, the ILP of the
generated code would not be easily extracted by the processor at
execution time. Dynamic renaming is limited in practice (since the
window od instructions is limited).
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