Re: Pitfalls in interference graph ?

Rayiner Hashem <rayiner@gmail.com>
Mon, 01 Oct 2007 23:48:58 -0700

          From comp.compilers

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From: Rayiner Hashem <rayiner@gmail.com>
Newsgroups: comp.compilers
Date: Mon, 01 Oct 2007 23:48:58 -0700
Organization: Compilers Central
References: 07-09-10407-10-003
Keywords: registers, optimize

> > I am trying to implement Briggs Optimistic register allocator after
> > reading the the thesis written by Preston Briggs.
>
> > Now for building the interference graph what other than register pairs
> > is there any other issues that one has to look out for?
>
> This a pretty old method of register allocation that do no longer work
> well. Indeed, it was designed for the case of sequential processors.
> Nowadays, processors implement instruction level parallelism. The
> register allocation problem changed, and the old graph coloring
> methods became useless.


Huh? Where is the dependence on sequential processing in graph
coloring allocation? Moreover, only a few non mainstream archs expose
non sequential semantics at the ISA level anyway.



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