Re: CFGs vs. "declare variable before use"

"Swapnajit Mittra" <mittra@juno.com>
8 Jun 2005 15:58:06 -0400

          From comp.compilers

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[5 earlier articles]
Re: CFGs vs. "declare variable before use" torbenm@diku.dk (2005-05-31)
Re: CFGs vs. "declare variable before use" gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-05-31)
Re: CFGs vs. "declare variable before use" devriese@cs.tcd.ie (Edsko de Vries) (2005-06-02)
Re: CFGs vs. "declare variable before use" cfc@shell01.TheWorld.com (Chris F Clark) (2005-06-02)
Re: CFGs vs. "declare variable before use" gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-06-04)
Re: CFGs vs. "declare variable before use" mefrill@yandex.ru (mefrill) (2005-06-04)
Re: CFGs vs. "declare variable before use" mittra@juno.com (Swapnajit Mittra) (2005-06-08)
Re: CFGs vs. "declare variable before use" sharp@cadence.com (2005-06-08)
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From: "Swapnajit Mittra" <mittra@juno.com>
Newsgroups: comp.compilers,comp.lang.verilog
Date: 8 Jun 2005 15:58:06 -0400
Organization: http://groups.google.com
References: 05-05-21605-05-221 05-05-231 05-06-021 05-06-023
Keywords: design

1. A variable in Verilog not declared but used is by default assumed to
be a scalar (i.e. width = 1) of one of the 'net' types (such as, wire,
tri, wor etc.). The actual net type can be modified by the compiler
directive `default_nettype (Section 3.5 and 19 of IEEE Std. 1364-2001).


2. The same LRM says (Section 3.2.2) that '(i)t is illegal to redeclare
a name already declared by a net, parameter or variable declaration.'


Given 1 and 2, it will be illegal to declare a variable after its use.


- Swapnajit.
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