Re: CFGs vs. "declare variable before use"

glen herrmannsfeldt <gah@ugcs.caltech.edu>
4 Jun 2005 15:06:34 -0400

          From comp.compilers

Related articles
[3 earlier articles]
Re: CFGs vs. "declare variable before use" torbenm@diku.dk (2005-05-28)
Re: CFGs vs. "declare variable before use" cfc@shell01.TheWorld.com (Chris F Clark) (2005-05-28)
Re: CFGs vs. "declare variable before use" torbenm@diku.dk (2005-05-31)
Re: CFGs vs. "declare variable before use" gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-05-31)
Re: CFGs vs. "declare variable before use" devriese@cs.tcd.ie (Edsko de Vries) (2005-06-02)
Re: CFGs vs. "declare variable before use" cfc@shell01.TheWorld.com (Chris F Clark) (2005-06-02)
Re: CFGs vs. "declare variable before use" gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-06-04)
Re: CFGs vs. "declare variable before use" mefrill@yandex.ru (mefrill) (2005-06-04)
Re: CFGs vs. "declare variable before use" mittra@juno.com (Swapnajit Mittra) (2005-06-08)
Re: CFGs vs. "declare variable before use" sharp@cadence.com (2005-06-08)
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From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Newsgroups: comp.compilers,comp.lang.verilog
Date: 4 Jun 2005 15:06:34 -0400
Organization: Compilers Central
References: 05-05-216 05-05-221 05-05-231 05-06-021
Keywords: syntax, design

(comp.lang.verilog added)


Chris F Clark wrote:


> glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:


>>It seems that verilog is one language that doesn't require a variable
>>to be declared before it is used.


> The actual rules about when variables must be declared are quite
> convoluted in Verilog. Some statements implicitly cause declarations
> of the referenced variables if they weren't already declared, others
> don't. However, if a variable is declared, it must be declared
> "lexically" before it is used (that is the declaration must appear in
> the source text before the use).


As I understand it, they don't have to be declared lexically before
use.


Because statements are not executed in order, but more or less in
parallel, it is easy to accidentally declare a variable lexically
later.


I often move code around to make it more readable, and sometimes don't
move the declaration.


This will all be a little confusing to comp.compilers readers, but
there are two important kinds of variables in verilog, and the
compiler needs to know which is which. One kind, reg variables, keep
there value when they are not being assigned, as do variables in most
programming languages. The other kind, wire variables, are used with
a continuous assignment statement, and so keep their value due to the
continuous assignment. If I say:


wire c;
assign c=!(a & b);


the logic is that of a 7400 style NAND gate. c changes soon after a
or b, just like a real NAND gate would work. The position of the
assign statement in the program (assuming a legal position) has no
effect on the logic.


It is supposed to work if the wire c; statement comes after the assign
statement.


-- glen



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