Re: CFGs vs. "declare variable before use"

glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:


> It seems that verilog is one language that doesn't require a variable
> to be declared before it is used.


The actual rules about when variables must be declared are quite
convoluted in Verilog. Some statements implicitly cause declarations
of the referenced variables if they weren't already declared, others
don't. However, if a variable is declared, it must be declared
"lexically" before it is used (that is the declaration must appear in
the source text before the use).


The essential problem is the Verilog has several roles to play. One
is a language written by humans to model circuit designs. Another use
of Verilog is as a "netlisting" language, that is a language to
capture the low level connections within a circuit. Netlists are
often machine generated programs. It is convenient to make such
netlists, not have to worry about "declarations" as it saves a pass in
the netlist creation program. As such, Verilog is one of the few
languages that is designed with machine generated code as one of its
primary formats.


Hope this helps,
-Chris


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Compiler Resources, Inc. Web Site : http://world.std.com/~compres
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