Re: How about VLIW used as RISC?

Ricardo Bugalho wrote:


> On Wed, 28 Apr 2004 15:33:26 -0400, Ron wrote:


>>So what is your opinion?


> VLIW is only interesting if you want to build a one way (one instruction
> word) in-order CPU. Anything else, plain old RISC is simpler.


To try to keep the subject compilers, instead of comp.arch, it seems
one should ask what is the best way to get the information that the
compiler knows about the instructions it is generating into the
hardware at the time they are needed.


Out of order execution is needed in case the compiler generated the
instructions in the wrong order (as needed by the processor).


On the other hand, the idea of an architecture independent of the
implementation only makes sense if you can compile without knowing the
specific implementation.


(Remember that machines IBM is building today will still execute
programs compiled or assembled 40 years ago for S/360.)


It seems that VLIW, even more than RISC, requires the compiler to know
too much about implementation details.


I suggest, then, compiling to an intermediate representation close to,
but not exactly, what the hardware needs to execute. An
implementation independent representation. At program load time the
code is examined and adapted to the specific implementation. For
example, the appropriate number of branch delay slots are filled in,
and instructions are reordered based on implementation specific
timing.


The final result may be VLIW, where each word contains many RISC type
instructions that can be executed at the same time.


Otherwise, I don't believe that a VLIW compiler written today could be
expected to generate code to run on a machine built 40 years from now.


-- glen
[Sounds like the S/38 and AS/400. -John]

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