How about VLIW used as RISC?

ronald@interqos.com (Ron)
28 Apr 2004 15:33:26 -0400

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How about VLIW used as RISC? ronald@interqos.com (2004-04-28)
Re: How about VLIW used as RISC? nmm1@cus.cam.ac.uk (2004-04-29)
Re: How about VLIW used as RISC? ricardo.b@zmail.pt (Ricardo Bugalho) (2004-04-29)
Re: How about VLIW used as RISC? torbenm@diku.dk (2004-04-29)
Re: How about VLIW used as RISC? MitchAlsup@aol.com (2004-04-29)
Re: How about VLIW used as RISC? alexc@std.com (Alex Colvin) (2004-05-02)
Re: How about VLIW used as RISC? gah@ugcs.caltech.edu (glen herrmannsfeldt) (2004-05-02)
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From: ronald@interqos.com (Ron)
Newsgroups: comp.arch,comp.compilers
Date: 28 Apr 2004 15:33:26 -0400
Organization: http://groups.google.com
Keywords: architecture, question, comment
Posted-Date: 28 Apr 2004 15:33:26 EDT

We have simple scalar RISC and superscalar RISC but why there is few
or no VLIW used as an RISC for general application? There is criticism
about code density. However, as many has pointed out, modern VLIW has
already used compression to remove NOOP instruction in the instruction
packet. I guess 40-bit instruction is enough hold the additional
control information, such as predicate bits, p bits(for indicating the
last instruction of the instruction packet).


So what is your opinion?
[Please try to keep this to compiler issues; comp.arch has a running
flamefest on the Itanium that you're all welcome to join. -John]

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