Re: compilers using MMX instructions in the generated code

andi@complang.tuwien.ac.at (Andreas Krall) writes:


> > In this example, I don't think you can vectorize both loops.
>
> It is possible to vectorize both loops. Our prototype compmiler for
> the SPARC VIS can handle this case (with a little bit support from the
> hardware). The SPARC has support for unaligned loads where only three
> instructions are necessary for an unaligned load


I was referring to vectorizing those loops on a proccessor like MMX,
which I believe requires 12-bit aligned loads, and has no support for
unaligned loads.


> Similar code can be emitted for processors without support by
> shifts and logical or.


However, you probably immediately revert to the same performance as
unvectorized on the MMX. But it would be worth analyzing.


-- g

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