Related articles |
---|
how do a RISC compiler translate an array initialization ? Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (1999-08-02) |
Re: how do a RISC compiler translate an array initialization ? zalman@netcom15.netcom.com (Zalman Stern) (1999-08-02) |
Re: how do a RISC compiler translate an array initialization ? toon@moene.indiv.nluug.nl (Toon Moene) (1999-08-04) |
Re: how do a RISC compiler translate an array initialization ? pmichaud@irisa.fr (1999-08-04) |
Re: how do a RISC compiler translate an array initialization ? Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (1999-08-04) |
Re: how do a RISC compiler translate an array initialization ? Sid-Ahmed-Ali.TOUATI@inria.fr (Sid Ahmed Ali TOUATI) (1999-08-07) |
From: | Zalman Stern <zalman@netcom15.netcom.com> |
Newsgroups: | comp.compilers,comp.arch |
Date: | 2 Aug 1999 14:56:07 -0400 |
Organization: | Netcom |
References: | 99-08-015 |
Keywords: | architecture |
In comp.arch Sid Ahmed Ali TOUATI <Sid-Ahmed-Ali.TOUATI@inria.fr> wrote:
: [Sounds like the cache lines are bigger than individual words, and these
: chips may have a write-behind cache. -John]
He took the cache line behavior into account. (REAL is 8 bytes, 200 of
them is 50 cache lines for a 32 byte line.) More likely the issue has
to do with how the performance counters work with respect to write
misses. A quick test is to measure the run time of the loop posted and
a loop which stores the constant to the same variable over and over
again. Checking the compiler output of course to make sure the stores
is not optimized away. In C/C++ you can declare the variable volatile
to defeat compiler optimization. I do not know if there is a similar
mechanism in FORTRAN.
-Z-
Return to the
comp.compilers page.
Search the
comp.compilers archives again.