how do a RISC compiler translate an array initialization ?

dear all,
I am playing with hardware performance mechanism of sparc II (and
pentium). These mechanisms are some specific purpose register for
counting some specific events (cache miss, latencies, lost cycles...).


I try to understand memory access behavior of a simple code like:


REAL X(200)
for i=1, 200
  x(i)=2 <----- or any constant value
end for


I thought that this is equivalent to access every X element in each
iteration, which yield to some cache miss equal to 50 in an ultra
sparc II. My surprise was that the real number of misses (counted with
specific registers) was about 3 or 4, with different compilers (cc,
gcc), different optimization (any, -O1..O4), different languages
(fortran, C). So, I analyzed the code generated, and it seems that
there is a memory access in each iteration. This does not explain why
cache misses does not occur. How does the compiler translate such
code of array assignment with a constant ? I turned off all
optimizations and the result is the same. So: 1. is there a mechanism
to store a constant value in a large data segment ? the code generated
seems to contain classic stores ("st" instructions). 2. Do the
compiler bypass the data cache when it generate an array
initialisation ? this is possible on some processors like the ultra
sparc.


thank you


Sid Ahmed Ali Touati


Remark: when I replace the instruction with x(i)=x(i)+1, a "relatively"
correct number of cache misses is reported (42 or 43 misses are
reported). It proove that the compilation process is not the same for
the first and the last version of the code despite the fact that I
turned off all optimization options.
[Sounds like the cache lines are bigger than individual words, and these
chips may have a write-behind cache. -John]

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