Re: Register allocation and instruction scheduling

David A. Greene (greened@zip.eecs.umich.edu) wrote:
: Is this really a problem, though? I was under the impression that
: a processor such as the PA 8K has a maximum number of in-flight
: instructions and the hardware resources such as the instruction
: buffer/reservation stations, execution units and physical registers
: are all tailored to this number.


A good counter example is the PowerPC 604 where a noticeable limit is
that there can only be six outstanding result registers at any given
time. As soon as you try to write the seventh register, the processor
stalls until one of the previous instructions retires. (This comes up
more often than you might expect because PowerPC's load-update
instructions produce two results.) This particularly offended me
because it means code that might run without hazards on an in-order 32
register RISC without renaming can experience stalls on the 604.


Not much for a compiler or human to do about this though. The
processor is pretty much setting a hard limit on the amount of work
you can do...


-Z-

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