Register allocation and instruction scheduling

mikesw@whiterose.net (Chris)
17 Jan 1999 20:46:33 -0500

          From comp.compilers
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Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-20)
Re: Register allocation and instruction scheduling greened@zip.eecs.umich.edu (David A. Greene) (1999-01-22)
Re: Register allocation and instruction scheduling bob.morgan@digital.com (1999-01-25)
Re: Register allocation and instruction scheduling mikesw@whiterose.net (1999-01-27)
Re: Register allocation and instruction scheduling zalman@netcom.com (1999-01-27)
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From: mikesw@whiterose.net (Chris)
Newsgroups: comp.compilers
Date: 17 Jan 1999 20:46:33 -0500
Organization: DataHaven Project, Inc (http://www.dhp.com)
Keywords: code, registers

Hi,
    I'm presently reading Appel's book on compilers and a few questions
came to mind.


1) How to take into account register renaming by the hardware by the
compiler: especialy when using graph coloring techniques?


2) How to take into account hardware instruction scheduling/reordering
when trying to do different types of compiler instruction optimzation.


Do I have to take into account register renaming and instruction
reordering when trying to design an optimized compiler?


Doesn't the hardware essentially undo all of my hard work in trying to
write an optimized compiler? The book doesn'talk about these topics.


Mike,
mikesw@whiterose.net

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