Re: Register allocation and instruction scheduling

On 22 Jan 1999 21:25:11 -0500, "David A. Greene"
<greened@zip.eecs.umich.edu> wrote:


>Aren't the limited capability of the execution units (if they are not
>uniform) and number of cache ports (or degree of overlapping) usually
>the main structural hazards? It seems a bit silly that a processor
>would run out of physical registers. Now a clustered register file is
>another issue entirely and there the compiler can help.


If we are trying to put resources on a chip there are always
limitations. Furthermore the bigger the register file, the slower the
access to registers and the more control structure controlling the
registers. So there are always limitations. The compiler must be
prepared to keep the limitations from hurting performance. In other
words there may not be enough physical registers to do any sequence of
instructions and register renaming situations.


In fact, it is probably a bad idea to have enough physical registers
for all situations. That ties of chip real estate and control logic
that would rarely be used. Instead you want enough physical registers
to guarantee that maximum performance can be gained and then have the
compilers gain that performance.


Bob Morgan

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