Re: Is there any generator generator, not parser generator?

Anton Ertl wrote:
>
> David Chase <chase@world.std.com> writes:
> > There are other ways to approach this; on a
> > machine with many registers (i.e., not x86) you could pessimistically
> > pre-allocate registers; during pattern- matching you'd discover that
> > you weren't using those registers after all, but you might do well
> > enough anyway. You could perform some amount of "semantic"
> > scheduling/pipelining, in which you simply assumed that each abstract
> > operation had a latency associated with it, and work from that;


> Why do these phases in the wrong order when you can do them in the
> right order? Just do instruction selection before instruction
> schedling and register allocation, and the problems mentioned above go
> away.


True, except that then your register allocation becomes more machine-
specific, spilling becomes more of a pain, and procedure prologues and
epilogues become a bit of a pain if you hope to do leaf, shrink- wrap,
or tail-call optimization (these depend on the machine quite a bit
anyway). The extra pain is the "right way" to do it if you have
plenty of time to do it that way, but I got the impression that the
original poster was looking for a less-pain solution.
Register-allocating early on a RISC machine is not going to hurt you
that badly if you aren't writing a scheduler anyway. (At least, that
is my gut evaluation of the problem, and there will always be odd
programs for which that statement is spectacularly wrong.)


David Chase
NaturalBridge LLC

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