Related articles |
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Is there any generator generator, not parser generator? baehj@oz.co.kr (Bae, Hyun-jik) (1998-10-13) |
Re: Is there any generator generator, not parser generator? chase@world.std.com (David Chase) (1998-10-17) |
Re: Is there any generator generator, not parser generator? dwight@pentasoft.com (1998-10-17) |
Is there any generator generator, not parser generator? KPRASAD@us.oracle.com (KPRASAD.US.ORACLE.COM) (1998-10-17) |
Re: Is there any generator generator, not parser generator? assmann@ipd.info.uni-karlsruhe.de (Uwe Assmann) (1998-10-17) |
Re: Is there any generator generator, not parser generator? anton@mips.complang.tuwien.ac.at (1998-10-18) |
Re: Is there any generator generator, not parser generator? chase@world.std.com (David Chase) (1998-10-21) |
From: | anton@mips.complang.tuwien.ac.at (Anton Ertl) |
Newsgroups: | comp.compilers |
Date: | 18 Oct 1998 23:16:05 -0400 |
Organization: | Institut fuer Computersprachen, Technische Universitaet Wien |
References: | 98-10-085 |
Keywords: | code, tools |
David Chase <chase@world.std.com> writes:
> There are other ways to approach this; on a
> machine with many registers (i.e., not x86) you could pessimistically
> pre-allocate registers; during pattern- matching you'd discover that
> you weren't using those registers after all, but you might do well
> enough anyway. You could perform some amount of "semantic"
> scheduling/pipelining, in which you simply assumed that each abstract
> operation had a latency associated with it, and work from that;
Why do these phases in the wrong order when you can do them in the
right order? Just do instruction selection before instruction
schedling and register allocation, and the problems mentioned above go
away.
There's still a phase ordering problem between scheduling and register
allocation, but if there are enough registers, doing register
allocation last will work well (there are lots of more complex methods
to deal with this).
In Section 4 of [ertl&pirker97] you can find a description of a basic
block code generator that uses tree parsing for instruction selection,
and performs instruction scheduling and local register allocation.
@InProceedings{ertl&pirker97,
author = {M. Anton Ertl and Christian Pirker},
title = {The Structure of a {Forth} Native Code Compiler},
booktitle = {EuroForth '97 Conference Proceedings},
year = {1997},
address = {Oxford},
pages = {107--116},
url = {http://www.complang.tuwien.ac.at/papers/ertl&pirker97.ps.gz},
abstract = {Writing a sophisticated Forth native code compiler
poses some tasks that are not discussed in compiler
text books. Some of these tasks arise from specific
language features, others from the requirement for
very fast compilation to maintain interactivity. In
this paper we describe some of the more interesting
data structures and algorithms used in the RAFTS
prototype.}
}
- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html
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