Re: Intel IA-64 Architecture

creedy@mitretek.org (Chris Reedy) wrote:


> Is it feasible to expect compilers to be able to do a good job of
> making use of this architecture? Is this a compiler writers nightmare
> (or dream)?


I think its a perfectly feasible idea. We have been researching a
similar problem area involving instruction scheduling for a minimal
superscalar, where instruction scheduling makes out-of-order issue
redundant and simplifies the architecture. Our current scheduler
achieves speedups in the range of 2.9-3.6, although some of this
speedup comes from the machine parallelism. For any architecure using
instruction scheduling once the problem of code compatibility has been
solved, the problem basically similar to that of scheduling a VLIW
architecture. There have been several examples of this including the
Multiflow, Cydra-5, iHARP, IBM's VLIW group etc.


The use of conditional/predicate execution allows the compiler to
convert control dependencies into data dependencies allowing many
further optimizations. The use of predicates allows you trade of fetch
efficiency against the capility to expose ILP along multiple execution
threads. The use of scheduling is only a nightmare as it expands
greatly the problem domain [See the Mutiflow paper below]. However, it
is a dream as it provides so much more scope for inovative problem
solving.


VLIW refs:


Beck, G.R. et al.:
"The Cydra-5 Mini-supercomputer: Architecture and Implementation", Journal
of Supercomputing, Vol. 7, Nos. 1/2, May 1993, pp143-181.


Lowney, P.G. et al.:
"The Multiflow Trace Scheduling Compiler", Journal of Supercomputing,
Vol.7, No. 1/2, May 1993, pp51-142


IBM's VLIW Group:
http://www.research.ibm.com/vliw/


iHARP
Steven, G.B.:
"iHARP: a Multiple Instruction Issue Processor", IEE Proceedings, Vol. 139,
No. 5, (September 1995), pp439-449


--
Richard Potter
Faculty of Engineering and Information Sciences,
University of Hertfordshire UK.
--

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