Intel IA-64 Architecture (Chris Reedy)
13 Nov 1997 23:41:36 -0500

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From: (Chris Reedy)
Newsgroups: comp.compilers
Date: 13 Nov 1997 23:41:36 -0500
Organization: Mitretek Systems
Keywords: optimize, question, architecture

I just read in the latest Byte magazine the description of the new
Intel IA-64 architecture. For those who may not have seen the article,
it has the following features (in brief, please read the article for
more details):

1. Each 128 bit bundle (word) contains three instructions (40 bit
fixed length).

2. Each instruction has associated with it explicit information as to
which other instructions can be executed in parallel.

3. Instructions have predicate information indicating whether the
instruction will have effect (maybe in the future). This is intended
to allow both alternatives of a branch to be executed with the correct
result being determined later.

4. There is a speculative load instruction that can be used to preload
information with exceptions being deferred until a subsequent check

The last two items where identified in the article as being designed
to allow for expansion of basic blocks.

The article also stated, more than once, that use of these features
depends on having the appropriate compiler support. In particular, the
CPU will not attempt to dynamically analyze the instruction stream to
determine parallelism but will depend on the compiler to have set the
correct flags within the instruction stream.

Is it feasible to expect compilers to be able to do a good job of
making use of this architecture? Is this a compiler writers nightmare
(or dream)?


Dr. Christopher L. Reedy, Mail Stop Z667
Mitretek Systems, 7525 Colshire Drive, McLean, VA 22102-7400
Email: Phone: (703) 610-1615 FAX: (703) 610-1603
[The VLIW people, most of whom used to be at Multiflow, have been working
on this problem for a decade, and there's some very good work. It pushes
a lot of work onto the compiler, but the optimization opportunities are
large. -John]


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