Re: The RISC penalty -- some real data (Jeff Jackson)
18 Dec 1995 19:14:34 -0500

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Re: The RISC penalty -- some real data (1995-12-18)
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From: (Jeff Jackson)
Newsgroups: comp.compilers
Date: 18 Dec 1995 19:14:34 -0500
Organization: I would rather be windsurfing.
References: 95-12-063 95-12-077
Keywords: architecture, performance

Here at Harris Computer Systems, we have a neat tool called analyze
which will, among other things, patch an existing executable with code
to do profile analysis. One of the types of profile analysis is does
is cache analysis. I took our native PowerPC 604 compiler and
simulated different sized primary caches while the compiler compiled
one of the larger files in its own source.

The purpose of this is to simulate doubling the size of PowerPC 604
instructions without encoding any additional control in the

The program execute 1.049370e+9 instructions.
With a 32Kb instruction cache, there were 4.727587e+6 misses (.45%)
With a 64Kb instruction cache, there were 1.810413e+6 misses (.17%)
With a 128Kb instruction cache, there were 0.751009e+6 misses (.07%)

Assuming a cache miss takes about on order of magnitude longer than a
cache hit, we might guess that there is about a 3% penalty for
doubling the size of the instructions on a machine with 64Kb
instruction cache. Looking at the data, doubling the size of the
instruction will increase the number of cache misses by a factor of
roughly 2.5 (yes, I know this isn't determined with large enough
sample for publishing in TOPLAS, but I don't get paid to write papers
for USENET :-). If a program is running 99% out of cache to begin
with, doubling the instruction size (effectively cutting the cache
size in half) is not that big a deal. If a program is running 90% out
of cache, we're probably starting to talk about a big deal.
Jeffrey Glen Jackson


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