Re: The RISC penalty

cdg@nullstone.com (Christopher Glaeser)
17 Dec 1995 00:16:56 -0500

          From comp.compilers
Related articles
The RISC penalty d.sand@ix.netcom.com (1995-12-09)
Re: The RISC penalty cdg@nullstone.com (1995-12-17)
Re: The RISC penalty pardo@cs.washington.edu (1995-12-18)
Re: The RISC penalty -- some real data jgj@ssd.hcsc.com (1995-12-18)
Re: The RISC penalty pardo@cs.washington.edu (1995-12-19)
Re: The RISC penalty jbuck@Synopsys.COM (1995-12-20)
Re: The RISC penalty pardo@cs.washington.edu (1995-12-21)
Re: The RISC penalty iank@dircon.co.uk (1995-12-28)
[4 later articles]
| List of all articles for this month |
From: cdg@nullstone.com (Christopher Glaeser)
Newsgroups: comp.compilers
Date: 17 Dec 1995 00:16:56 -0500
Organization: Compilers Central
References: 95-12-063
Keywords: architecture, performance, comment

Duane Sand <d.sand@ix.netcom.com> writes:
> He says the main problem is the
> excessive number of code cache misses caused by the poor code density
> of RISC code. He calls the whole RISC architecture thing a fad, ...


Which micro-architecture did he use to evaluate his performance (e.g. 601,
603, 603e, 604)? The PowerPC architecture does not define a cache design;
these parts have different cache designs which have significant impact
on cache-sensitive applications.


Regards,
Christopher Glaeser cdg@nullstone.com
Nullstone Corporation
[I looked at the article. The main application the guy is working on is the
68K emulator, and I can't say I'm amazed at his discovery that 68K chips are
better at running 68K object code than RISCs are. -John]
--

Post a followup to this message

Return to the comp.compilers page.
Search the comp.compilers archives again.