Second CFP : Cosynthesis for reconfigurable systems

                                        Second Call for Papers


                                                IEE Colloquium
          Hardware-software cosynthesis for reconfigurable systems
                                            February 22, 1995.


System architectures that incorporate field programmable hardware as
well as ``conventional'' ASIC and microprocessor parts are becoming
increasingly popular. Systems such as these promise improved time to
market, painless field-upgrades, and through dynamically
reprogrammable hardware, applications that optimise their own hardware
at runtime. This colloquium, the third in the IEE Hardware-software
codesign series, is to address the challenge of synthesising such
systems. Papers are invited on all aspects of synthesising reliable
and maintainable reconfigurable systems. Papers that address toolkits
for cosynthesis, and illustrate methodologies through case studies
will be particularly welcome. The colloquium will be held at
Hewlett-Packard Research Laboratories, Bristol, England.


Submissions should consist of three copies of a 700 to 1000 word
summary including a short description of the problem and its
significance with references to previous work, plus the title,
authors' names, affiliations, addresses, topic category, telephone and
facsimile numbers, and e-mail addresses if available.


The deadline for submissions is December 8, 1995. Authors will be
notified of acceptance by December 20, 1995 and full papers will be
due by January 19, 1995.


For further details please contact Richard Taylor, Hewlett-Packard
Laboratories, Filton Road, Bristol BS12 6QZ, UK. Phone (44) 117 922
9545, Email rwt@hpl.hp.com. or Claire Coleshill, IEE, Savoy Place,
London, WC2R 0BL, United Kingdom. Phone (44) 171 344 5419, Fax (44)
171 497 3633, Email : ccoleshill@iee.org.uk
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