IEE Colloquium : Verification of hardware-software codesigns

IEE Colloquium.
--------------
Verification and Validation of Hardware/Software Codesigns


The second one day colloquium in the IEE "Hardware/Software Codesign"
series, 'Verification of hardware-software codesigns' is being
organised by PG C2 (Hardware and Systems Engineering) and PG C6
(Systems Engineering for Automation) at Savoy Place, London on Tuesday 17
October 1995.


Codesign refers to the simultaneous process of designing both hardware
and software to meet some specified performance objectives. Unlike
more traditional approaches to system engineering where the hardware
and software partitions are relatively rigid, codesigns are
characterised by flexible partitions that may be shifted to meet
changing performance criteria. One consequence of this is that
sophisticated and flexible specification, synthesis, verification &
validation tools become essential to the design process.


The first colloquium in this series addressed current research and
practice in the area of partitioning codesigns. The purpose of this
colloquium is to examine the verification and validation processes
essential for effective hardware-software codesign. Papers being
presented at this colloquium address the requirements for verification
and validation procedures, formal models for describing codesigns, and
practical tools for their realisation. Speakers have been drawn from
across Europe.


The morning session will concentrate on models and formalisms for
codesigns. After lunch, experimental toolsets for design exploration,
validation and verification will be presented. The colloquium will
conclude with a panel session addressing the practical problems of
migrating laboratory tools and techniques to industrial applications.


For further details and registration, please contact Claire Coleshill,
IEE, Savoy Place, London, WC2R 0BL, United Kingdom. Phone (44) 171 344
5419, Fax (44) 171 497 3633, Email : ccoleshill@iee.org.uk


*************** Program **********************


Chair : R Taylor, Hewlett-Packard Laboratories, Bristol, England.


10.00 - 10.30 Registration and Coffee


10.30 - 11.00 T Ismail and A Jerraya, TIMA/INPG Grenoble, France,
``Design Models and Steps for Codesign''


11.00 - 11.30 R Nicholls, Manchester Metropolitan University,
Manchester, ``Verification or Validation of Hardware/Software
Codesigns ?''


11.30 - 12.00 N Jayaramn, University of Westminster, London,
``Verification of Real Time Systems - Issues and Perspectives''


12.00 - 12.30 J Staunstrup, Technical University of Denmark, Denmark,
``Interface Models in Hardware/Software Codesigns''


12.40 - 1.30 Lunch


1.30 - 2.00 M Sheeran, Chalmers Technical University, Sweden , S
Singh, Glasgow University, Scotland , ``Ruby as a Basis for
Hardware/Software Codesign''


2.00 - 2.30 W Luk and Peter Cheung, Imperial College of Science,
Technology and Medicine, London, ``A Toolkit for Exploring
Hardware/Software Systems''


2.30 - 3.00 W Rosentiel, University of T'ubingen and Forshungszentrum
Informatik, Germany, ``Source Level Emulation to Bridge the Gap
Between High Level Synthesis and Emulation''


3.00 - 3.30 G Evans and D Morris, UMIST, Manchester, ``Validation and
Verification of System Designs using MOOSE''


3,30 - 3.45 Coffee


3.45 - 4.45 Panel Discussion ``Transferring Laboratory Techniques to
Industry, Requirements, Aspirations and Practicality'', Chair : J
Harrison, Hewlett-Packard Limited


4.45 Close






--
Richard Taylor,
Hewlett-Packard Laboratories, Bristol, UK.
rwt@hplb.hpl.hp.com
phone : +44 (0) 117 922 9545
fax : +44 (0) 117 922 8925
--

Return to the comp.compilers page.
Search the comp.compilers archives again.