Re: Optimizing assembler for SPARC

Mark Leone <mleone+@cs.cmu.edu> wrote:
>Beware: the MIPS assembler has similar problems. It assumes that the
>so-called temporary registers ($t0-$t9) are never live across procedure
>calls. [...]
>
>Is there a way to defeat this behavior (other than .set nomove)? Are
>there any "general purpose" MIPS schedulers out there?


Michael Meissner pointed me in the right direction: later versions of
the MIPS assembler (e.g. 2.1) provide a ".livereg" directive that is
documented in Kane and Heinrich's 1992 architecture reference:


.livereg indicates to the assembler which registers are live
before a jump, to avoid unsafe optimizations by the
reorganizer. The directive .livereg takes two arguments,
int_bitmask, and fp_bitmask, which are 32-bit bitmasks with a
bit turned on for each register that is live before a jump.
The most significant bit (!) corresponds to register $0....


--
Mark Leone <mleone@cs.cmu.edu>
School of Computer Science, Carnegie Mellon University
Pittsburgh, PA 15213 USA
--

Return to the comp.compilers page.
Search the comp.compilers archives again.