Re: "Delayed" instructions on the MIPS/SPIM simulator

larus@cs.wisc.edu (James Larus)
Mon, 23 May 1994 14:01:32 GMT

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"Delayed" instructions on the MIPS/SPIM simulator jhummel@cy4.ICS.UCI.EDU (Joe Hummel) (1994-05-21)
Re: "Delayed" instructions on the MIPS/SPIM simulator larus@cs.wisc.edu (1994-05-23)
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Newsgroups: comp.compilers,comp.arch
From: larus@cs.wisc.edu (James Larus)
Keywords: architecture, tools
Organization: U of Wisconsin CS Dept
References: 94-05-083
Date: Mon, 23 May 1994 14:01:32 GMT

Joe Hummel <jhummel@cy4.ICS.UCI.EDU> writes:
|> We're using the SPIM simulator (freely available from Prof. Larus at the
|> U. of Wisconsin) in an undergraduate architecture class. I'd like the
|> students to have a chance to use the delayed branch and load instructions
|> available on the MIPS. [The documentation is sparse.]


In "bare mode," you get exactly what the MIPS R2000/R3000 hardware
provides and no more (see Kane for more details): all control transfers
(branches, jumps, jump and links) are delayed a single cycle and all loads
are delayed a single cycle (with NO hardware interlock). In the normal
mode of SPIM, neither class of instruction is delayed (as in the assembler
model). Moreover, in bare mode you do not have the assembler-extended
instruction set that makes the MIPS a joy to program.


/Jim
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