Pipeline Descriptions

todd@cs.arizona.edu (Todd A. Proebsting)
Sun, 15 Aug 1993 17:05:13 GMT

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Pipeline Descriptions todd@cs.arizona.edu (1993-08-15)
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Newsgroups: comp.arch,comp.compilers
From: todd@cs.arizona.edu (Todd A. Proebsting)
Keywords: architecture, optimize, question
Organization: University of Arizona CS Department, Tucson AZ
Date: Sun, 15 Aug 1993 17:05:13 GMT

I need complete pipeline descriptions for modern architecture
implementations (e.g., MIPS R3000, MIPS R4000, SPARC incarnations,
PowerPC, PA-RISC, i860, etc.) These descriptions will be used as the
basis for a high-level specification that will then be compiled into an
instruction scheduler.

A pipeline description is given on a per instruction basis and defines
which machine resources are used at each cycle of a machine's execution.
For instance, on the R4000, the add.s instruction's description might look

U; S,A; A,R; R,S;

add.s requires exclusive access to the U (for ``unpack'') stage in cycle
0, the S (for ``shift'') and A (for ``adder'') stages in cycle 1, A and R
(for ``round'') in cycle 2, and R and S in cycle 3. (This information
comes from Tables 8-7 and 8-8 in Kane's 1992 MIPS RISC Architecture book.)
"Reservation tables" contain similar information.

A complete pipeline description would include this data as well as bypass
and interlock information.

Unfortunately, I have been unable to locate exact pipeline descriptions
for most machines. (Kane, for instance, is not so exact on the FPU of the
R3000, nor on the integer instructions of the R4000.)

If you know where this information can be found for any current
architecture implementation, please let me know. I will summarize what I

Todd Proebsting

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