Summary: Instruction Scheduling References

About 3 weeks ago I asked for books, articles etc. about instruction
scheduling. Although I asked for published *or* unpublished material,
my focus was on unpublished articles and those which are hard to find,
like [B+] (which is unpublished and not referenced anywhere) or
[Kas90] (where not even once the word scheduling is mentioned).


Therefore with this posting I want to


thank the listed contributors for the listed references,


*and*


encourage everyone to complete the list of instruction scheduling references.




Contributors:
-------------
Erich Nahum
Mark Smotherman
Mario Wolczko
Chris Fraser
Nir Baroz
Anton Ertl




References:
-----------
[B+ ] Nir Baroz et al. An instruction scheduler for our company's CPU
running on our own real-time O.S. - MPX-32. Postprocessing utility
using a library of "perfectly scheduled mathematical functions".


[BEH91] David G. Bradlee, Susan J. Eggers, and Robert R. Henry. Integrating
register allocation and instruction scheduling for RISCs. In Proceed-
ings of the International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS), pages
122-131, Santa Clara, California, April 8-11 1991.


[BG89] D. Benstein and I. Gertner. Scheduling expressions on a pipelined
processor with a maximal delay of one cycle. ACM Transactions on
Programming Languages and Systems, 11(1), January 1989.


[BHE91] David G. Bradlee, Robert R. Henry, and Susan J. Eggers. The mar-
ion system for retargetable instruction scheduling. In Proceedings
of the ACM SIGPLAN International Conference on Programming
Language Design and Implementation, volume 26, pages 229-240,
Toronto, Ontario, Canada, June 26-28 1991. Association for Com-
puting Machinery (ACM).


[BR91] David Bernstein and Michael Rodeh. Global instruction schedul-
ing for superscalar machines. In Proceedings of the ACM SIGPLAN
International Conference on Programming Language Design and Im-
plementation, volume 26, pages 241-255, Toronto, Ontario, Canada,
June 26-28 1991. Association for Computing Machinery (ACM).


[Fis81] Joseph A. Fischer. Trace scheduling: A technique for global mi-
crocode compaction. IEEE Transactions on Computers, 30(7):478-
490, July 1981.


[GH88] J.R. Goodman and W. C. Hsu. Code scheduling and register al-
location in large basic blocks. In Proceedings of the International
Conference on Supercomputing, pages 442-452, St. Malo, France,
July 1988.


[Gla90] D.N. Glass. Compile-time instruction scheduling for superscalar pro-
cessors. In Proc. COMPCON, pages 630-633, San Francisco, CA,
Spring 1990.


[GM86] Phillip B. Gibbons and Steven S. Muchnick. Efficient instruction
scheduling for a pipelined architecture. In Proceedings of the ACM
SIGPLAN International Conference on Programming Language De-
sign and Implementation, pages 11-16, 1986.


[GR90] M. C. Golumbic and V. Rainish. Instruction scheduling beyond basic
blocks. IBM Journal of Research and Development, 34(1):93-97,
January 1990.


[HG83] John Hennessy and Thomas Gross. Postpass code optimization of
pipeline constraints. ACM Transactions on Programming Languages
and Systems, 5(3):422-448, July 1983.


[Jai91] Suneel Jain. Circular scheduling: A new technique to perform soft-
ware pipelining. In Proceedings of the ACM SIGPLAN International
Conference on Programming Language Design and Implementation,
volume 26, pages 219-228, Toronto, Ontario, Canada, June 26-28
1991. Association for Computing Machinery (ACM).


[Kas90] Uwe Kastens. "Ubersetzerbau, volume 3.3 of Handbuch der Infor-
matik, chapter 8.5 Anordnung von Instruktionen, pages 218-230.
Oldenbourg Verlag GmbH, M"unchen, Germany, 1990. written in
german.


[Kri90] S. Krishnamurthy. A brief survey of papers on scheduling for
pipelined processors. SIGPLAN Notices, 25(7):97-106, July 1990.


[Lam88] Monica Lam. Software pipelining: An effective scheduling tech-
nique for VLIW machines. In Proceedings of the ACM SIGPLAN
International Conference on Programming Language Design and Im-
plementation, pages 318-328. Association for Computing Machinery
(ACM), 1988.


[LKB91] Roland L. Lee, Alex Y. Kwok, and Faye A. Briggs. The floating-point
performance of a superscalar SPARC processor. In Proceedings of the
International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS), pages 28-37, Santa
Clara, California, April 8-11 1991.


[PF91] Todd A. Proebstring and Charles N. Fischer. Linear-time, opti-
mal code scheduling for delayed-load architectures. In Proceedings
of the ACM SIGPLAN International Conference on Programming
Language Design and Implementation, volume 26, pages 241-256,
Toronto, Ontario, Canada, June 26-28 1991. Association for Com-
puting Machinery (ACM).


[PS90] Krishna V. Palem and Barbara B. Simons. Scheduling time-critical
instructions on RISC machines. In Proceedings of the ACM Sympo-
sium on Principles of Programming Languages, pages 270-280, 1990.


[RF91] John C. Ruttenberg and Stefan M. Freudenberger. Phase ordering of
register allocation and instruction scheduling. In Proceedings of the
International Workshop on Code Generation, volume ??? of Lecture
Notes in Computer Science (LNCS), pages ??-?? Schloss Dagstuhl,
Germany, May 1991.


[Rym82] J. Rymarczyk. Coding guidelines for pipelined processors. In Pro-
ceedings of the International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS), pages
12-19, March 1982.


[SKAH91] Marc Smotherman, S. Krishnamurthy, P. S. Aravind, and D. Hun-
nicutt. Efficient DAG construction and heuristic calculation for in-
struction scheduling. Technical report, Department of Computer
Science, Clemson University, Clemson SC, June 1991.


[War90] H. S. Warren, Jr. Instruction scheduling for the IBM RISC sys-
tem/6000 processor. IBM Journal of Research and Development,
34(1):85-92, January 1990.
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