Looking for references and experts on optimizing compilers

After years of working on hardware design tools, I have become involved with
theoretical and practical aspects of implementing highly optimizing compilers.
In hardware CAD, it is frequently the case that the tools run for many CPU
hours, and this makes the customers unhappy. They would like to have
the software run in much less time. One of the things this suggests
is that the software should be made to run on parallel hardware.


In evaluating the cost/benefit ratio of parallelization, the question of
whether compilers can do the optimization for us arose, along with the
question of how well a compiler could do the job. This rekindled
my personal interest in the field of compilation, so I have been trying to
learn about the state of the art in parallelizing/pipelining compilers.


My request has two parts:


1. If anyone knows of good references to papers discussing theory
        and practice, please advise me. Especially the practical aspects,
        such as good data structures for representing programs (large
        programs, by the way), successful heuristics for transforming the code
        and empirically tested rules for ordering their application,
        expected amounts of memory and MIPS required, expected degree
        of pipelining or parallelizing to be attained, etc. I would take
        on-line copies of papers, too.


2. I'd also like to know who are the true experts in this area; i.e.,
        people with strong theoretical backgrounds, or especially people who
        have successfully implemented highly optimizing compilers for some of
        the newer pipelined RISC machines, or (say) the i860 or a hyper-cube.
        I am interested in learning about their experiences with the various
        newer architectures. I'm also interested in their opinions about manual
        vs. automated pipelining/parallelizing.


Any information will be gratefully appreciated. Please reply via e-mail.
Thanks!


        Thomas W. Kronmiller twk@cadence.com
        Manager, System Architecture
        Software Development Environment Ph. 408-987-5479
        Cadence Design Systems, Inc. FAX 408-727-5049

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