Re: How to eliminate redundant constant move instructions

amker <amker.cheng@gmail.com>
Tue, 1 Nov 2011 21:04:24 -0700 (PDT)

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[2 earlier articles]
Re: How to eliminate redundant constant move instructions gneuner2@comcast.net (George Neuner) (2011-11-01)
Re: How to eliminate redundant constant move instructions gah@ugcs.caltech.edu (glen herrmannsfeldt) (2011-11-01)
Re: How to eliminate redundant constant move instructions can.finner@gmail.com (amker) (2011-11-01)
Re: How to eliminate redundant constant move instructions can.finner@gmail.com (amker) (2011-11-01)
Re: How to eliminate redundant constant move instructions can.finner@gmail.com (amker) (2011-11-01)
Re: How to eliminate redundant constant move instructions amker.cheng@gmail.com (amker) (2011-11-01)
Re: How to eliminate redundant constant move instructions amker.cheng@gmail.com (amker) (2011-11-01)
Re: How to eliminate redundant constant move instructions gneuner2@comcast.net (George Neuner) (2011-11-02)
Re: How to eliminate redundant constant move instructions acolvin@efunct.com (mac) (2011-11-03)
Re: How to eliminate redundant constant move instructions kaz@kylheku.com (Kaz Kylheku) (2011-11-03)
Re: How to eliminate redundant constant move instructions gah@ugcs.caltech.edu (glen herrmannsfeldt) (2011-11-03)
Re: How to eliminate redundant constant move instructions gneuner2@comcast.net (George Neuner) (2011-11-04)
Re: How to eliminate redundant constant move instructions gah@ugcs.caltech.edu (glen herrmannsfeldt) (2011-11-04)
[4 later articles]
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From: amker <amker.cheng@gmail.com>
Newsgroups: comp.compilers
Date: Tue, 1 Nov 2011 21:04:24 -0700 (PDT)
Organization: Compilers Central
References: 11-10-019 11-11-004 11-11-005
Keywords: optimize

On Nov 2, 6:35 am, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
> That is what register renaming is for. Usually using more than
> the architecturally specified number of registers, the CPU
> internally remaps the registers such that it can keep one value
> in a register while an instruction is being executed out of order.


For this specific case, I previous intention was optimizing codes


rx <- 0
...
use rx
...
ry <- 0
use ry


into


rx <- 0
...
use rx
...
use rx


In this manner, I guess the register renaming won't help,
since the transformation introduces true dependency, right?




> Now, how to choose the > weights when one doesn't know the specific
target processor? > That is a good question.


How could this happen if middle end does not know the specific
processor? What I can image is there should be a way in which
back end provides information.


Thanks



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