Re: Compiler or interpreter?

BGB / cr88192 <cr88192@hotmail.com> wrote:
(snip, I wrote)


>> Note the quote above. The different implementations can be faster
>> or slower, even on different versions of the same architecture.
>> Among others, the branch prediction logic may be sensitive
>> to the differences.


> possibly, but I suspect matters are more basic:
> it takes several operations to decode arguments.


> for example:
> op=*ip++;
> if(op>=192)op=((op-192)<<8)|(*ip++); //naively handle multi-byte ops
> switch(i)


(big snip)


As far as I know, the usual implementation of switch/case, at least
with dense packing of cases, is either an indexed branch to a table of
branch instructions, or an indexed load followed by a register branch
instruction.


Not having followed branch prediction logic too recently, (I suppose
comp.arch is where that would go) it would seem that both cases are
difficult for branch prediction, but that the former would be a little
easier to process.


That is, one could build branch prediction logic that understood that
the value in a register was being used in an indexed branch and use
that register for prediction. Though another possibility would be to
provide an explicit switch/case instruction in the architecture.


-- glen

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