Related articles |
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[34 earlier articles] |
Re: New assembly language instructions to support OO languages? jasen@xnet.co.nz (Jasen Betts) (2008-12-11) |
Re: New assembly language instructions to support OO languages? first@last.name (Morten Reistad) (2008-12-12) |
Re: New assembly language instructions to support OO languages? torbenm@pc-003.diku.dk (2008-12-12) |
Re: New assembly language instructions to support OO languages? johnzabroski@gmail.com (John \Z-Bo\Zabroski) (2008-12-13) |
Re: New assembly language instructions to support OO languages? bear@sonic.net (Ray Dillinger) (2008-12-13) |
Re: New assembly language instructions to support OO languages? jasen@xnet.co.nz (Jasen Betts) (2008-12-14) |
Re: New assembly language instructions to support OO languages? gavin@allegro.com (2008-12-16) |
From: | gavin@allegro.com (Gavin Scott) |
Newsgroups: | comp.compilers,comp.arch |
Followup-To: | comp.arch |
Date: | Tue, 16 Dec 2008 19:44:11 -0600 |
Organization: | You expect organization? |
References: | 08-12-014 08-12-082 |
Keywords: | architecture, OOP |
Posted-Date: | 18 Dec 2008 17:25:20 EST |
In comp.arch Ray Dillinger <bear@sonic.net> wrote:
> If I had my druthers, I'd add a number of VERY wide registers
> replacing on the chip die the "implicit" registers known as cache
> lines and make the management of these explicit with its own
> instructions rather than implicit and heuristic.
How many of such registers would you want? Making them explicitly
visible registers bulks up your context switch saved-state.
Or is there an opportunity to re-introduce instructions that operate
directly on memory and support large data types / SIMD that happen to
execute extremely efficiently if the operands match cache line
size and alignment?
G.
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