From: | David W Schroth <David.Schroth@unisys.com> |
Newsgroups: | comp.compilers,comp.arch |
Date: | Fri, 05 Dec 2008 14:37:15 -0600 |
Organization: | Unisys - Roseville, MN |
References: | 08-12-014 08-12-017 08-12-021 |
Keywords: | architecture, comment |
Posted-Date: | 05 Dec 2008 18:47:02 EST |
Hans-Peter Diettrich wrote:
> Michael Tiomkin schrieb:
>
>
>> I understand that some ancient computers (in the 2nd millennium)
>>used segmented memory. If we could implement this and show that it
>>runs most of the programs faster, somebody would be able to build such
>>a processor.
>
>
> A segmented model requires possibly huge address translation tables,
> which have to reside in the cache. Unfortunately loading these tables
> on context switches (threads...) or on loading segment registers
> resulted in very poor runtime behaviour. The page concept (flat model)
> reduces the reloads to situations which require I/O (swap file), so
> that adjustments to the tables are neglectable.
The only way I can make sense of these (dubious) assertions is to assume
that you have a specific implementation in mind.
The system I work on is both segmented and paged. The Page Table
(note singular) consumes only a small fraction of memory. Being a
global Page Table, there is no penalty incurred when switching
threads. The time to load a segment register is a few cycles, and
doesn't seem to normally impact performance.
I can't make any sense of your last sentence no matter how I try.
David W. Schroth
[I expect he's thinking of the segmentation on x86 chips, which has rather
bad performance. Segment register loads are very slow, and since there
aren't very many seg registers, there were a lot of loads. -John]
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