Re: New assembly language instructions to support OO languages?

bert <bert.hutchings@btinternet.com> writes:


> On 4 Dec, 18:09, "Tony" <t...@my.net> wrote:
> > To me, it seems like "reducing everything to a function" may be a bit
> > dated given that OO languages are the thing nowadays. Can anyone
> > imagine any new potential assembly language instructions that would
> > make implemention of OO languages easier? (Not just necessarily the
> > function thing, but anything).


Well, its not a real machine, but here's an opcode description from my
current bytecode system:


        bc_gmeth, /* Get METHod. The top-of-stack is the reference to an
interface or capsule. The method vector is loaded
from offset 16 in the interface or capsule. Then,
the single 16 bit argument is added to the vector
address, and the actual method reference is loaded
from there. */


I can't see it being worth adding to a real CPU, however - it would
pipeline badly (two serialized fetches) and is trivial to build out of
existing instructions.


> [Indirect addressing was quite common through the 1970s. The PDP-11
> and VAX had it. But I gather that it's a challenge to implement
> efficiently, and if the machine has a lot of registers, it doesn't gain
> you much. -John]


Eh? I'm pretty sure the PDP-11 did not have an indirect bit. The PDP-8
or PDP-7 may have. I don't think the PDP-9 did, but I'm hazy on that one.
One machine I know has it is the Tera MTA (their earlier custom processor,
not the Opterons they use nowadays).


[The PDP-4, -5, -7, -8, -9, -11, and -15 had one-level indirect
addressing with the indirect bit in the instruction. The -6 and -10
had multilevel indirection with an indirect bit in both the
instruction and the address words. On the -6 and -10 the address was
considerably shorter than the word size. I did various tricky things
with indirect chains on the -10, although I doubt they'd perform well
on a modern machine with caches and pipelines. -John]

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