|instruction bundling (scheduling?) email@example.com (kphillips) (2008-04-04)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (2008-04-06)|
|Re: instruction bundling (scheduling?) email@example.com (kphillips) (2008-04-09)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (2008-04-13)|
|Re: instruction bundling (scheduling?) email@example.com (IndianTechie) (2008-04-14)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (kphillips) (2008-04-15)|
|Re: instruction bundling (scheduling?) SidTouati@inria.fr (Sid Touati) (2008-04-22)|
|Date:||Mon, 14 Apr 2008 22:18:40 -0700 (PDT)|
|References:||08-04-017 08-04-025 08-04-034 08-04-050|
|Posted-Date:||15 Apr 2008 13:54:29 EDT|
On Apr 13, 10:49 pm, andreybokha...@gmail.com wrote:
> On Apr 9, 11:29 pm, kphillips <kevin.phillip...@yahoo.com> wrote:
> > One other query - I have no specific algorithms that cater for data
> > prefetches. Since a load instruction take a huge amount of cycles
> > (assuming the worst case scenario - memory), is it a good idea to
> > issue advanced load instructions as early as possible? Then the
> > latency for loads will be assumed for quite less .. hopefully it will
> > work for most cases.
yes -unlike its competitor POWER processor, the itanium processor
depends on the compiler to pre-fetch data. Further, there is no on-
chip scheduler and so best results can only be obtained if compiler
writer schedules instructions appropriately.
> ...and registers' live ranges will be quite longer, leading to higher
> register pressure. You have to use a heuristic here.
> Regarding scheduling vs register allocation -- I agree with Anton Ertl
> that it is better to do scheduling first. For two reasons:
> 1. Usually, optimal, unhindered (by new dependencies introduced by
> register allocation) scheduling is more important (no hard data here,
> just my practical observations)
The APIC bundle was designed to schedule instructions in parallel in
such a way that processor utilization can be improved. If you know
that 2 or more instructions can safely execute in parallel either
because they use different functional units with the processor or
because there is no read-write conflict, just bundle them together.
> 2. You have quite a few registers on Itanium (especially if you
> allocate on single basic blocks level and thus, have all of the
> registers free again at the start of each new block)
we have quite a few registers on Itanium and there is a register
stack, wherein when you enter a procedure -local variables are
allocated on the register stack and then de-allocated when you exit.
So, the liveness of a variable(register allocation) is of concern only
within a procedure's context.
p.:s- I work for a company that sells Itanium boxes/compilers.
Return to the
Search the comp.compilers archives again.