|instruction bundling (scheduling?) firstname.lastname@example.org (kphillips) (2008-04-04)|
|Re: instruction bundling (scheduling?) email@example.com (2008-04-06)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (kphillips) (2008-04-09)|
|Re: instruction bundling (scheduling?) email@example.com (2008-04-13)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (IndianTechie) (2008-04-14)|
|Re: instruction bundling (scheduling?) email@example.com (kphillips) (2008-04-15)|
|Re: instruction bundling (scheduling?) SidTouati@inria.fr (Sid Touati) (2008-04-22)|
|Date:||Wed, 9 Apr 2008 12:29:07 -0700 (PDT)|
|Posted-Date:||10 Apr 2008 23:27:22 EDT|
Many thanks for your feedback!
> Given the large number of registers in IA-64, for simplicity just
> schedule first and allocate registers later; spilling and thus
> rescheduling will be rare. Also, most liveness analysis and register
> allocation algorithms work on scheduled code anyway (if they work
> before instruction scheduling, they use the order coming out of
> earlier phases).
Great. If there is the need for spilling, I will try either to
(1) try to find an empty slot in a template to use
(2) otherwise add an extra template for the load
It's rather simple, but I think it will work
> A nice paper on instruction scheduling and register allocation for
> basic blocks is:
> author = "James R. Goodman and Wei-Chung Hsu",
> title = "Code Scheduling and Register Allocation in Large Basic Blocks",
Thanks! will go through it very soon.
One other query - I have no specific algorithms that cater for data
prefetches. Since a load instruction take a huge amount of cycles
(assuming the worst case scenario - memory), is it a good idea to
issue advanced load instructions as early as possible? Then the
latency for loads will be assumed for quite less .. hopefully it will
work for most cases.
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