Re: Pitfalls in interference graph ?

Jeremy Wright <jeremy.wright@microfocus.com>
Tue, 2 Oct 2007 12:51:32 +0000 (UTC)

          From comp.compilers

Related articles
[2 earlier articles]
Re: Pitfalls in interference graph ? torbenm@app-1.diku.dk (2007-10-01)
Re: Pitfalls in interference graph ? johnl@iecc.com (2007-10-01)
Re: Pitfalls in interference graph ? bergner@vnet.ibm.com (Peter Bergner) (2007-10-01)
Re: Pitfalls in interference graph ? marcov@stack.nl (Marco van de Voort) (2007-10-01)
Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-01)
Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-01)
Re: Pitfalls in interference graph ? jeremy.wright@microfocus.com (Jeremy Wright) (2007-10-02)
Re: Pitfalls in interference graph ? shafitvm@gmail.com (shafi) (2007-10-15)
Re: Pitfalls in interference graph ? torbenm@app-6.diku.dk (2007-10-17)
Re: Pitfalls in interference graph ? SidTouati@inria.fr (ST) (2007-10-18)
Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-21)
Re: Pitfalls in interference graph ? Sid.Touati@uvsq.fr (Sid Touati) (2007-10-24)
Re: Pitfalls in interference graph ? parthaspanda22@gmail.com (2007-10-24)
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From: Jeremy Wright <jeremy.wright@microfocus.com>
Newsgroups: comp.compilers
Date: Tue, 2 Oct 2007 12:51:32 +0000 (UTC)
Organization: Posted via Supernews, http://www.supernews.com
References: 07-10-017
Keywords: registers, optimize

>> To preferentially assign a virtual register to a specific machine
>> register, rewrite the instruction to use the real register, and
>> prepend a copy virtual -> real / append a copy real -> virtual. If
>> the virtual register can safely be assigned to that real register,
>> the coalescing phase will do this and eliminate the copy. This works
>> for call parameters, call results, and ops that only take a specific
>> register.
>>
> How do you specify an affinity that is not 100% necessary? Like older
> i386 arch CPU's having a preference for EBX as index register ?


Now we really are into the pitfalls.


There is a similar situation on the PowerPC. An operation of the form


        ADD vr201 := gr200, -5


        where vr = virtual register


can be done using the Power instructions ai vr201,vr200,-5 ; or cal
vr201,-5(vr200). The latter form is preferable as it does not affect
the carry bit, allowing greater freedom for scheduling. However, if
one uses cal then vr200 cannot be assigned to gr0.


Smith and Holloway in "Graph-Coloring Register Allocation for
Irregular Architectures" describes how they implemented graph coloring
on x86 ISA. Quickly rereading, they do not seem to deal specifically
with the question of preferentially assigning ebx, but I may have
missed something. Interesting reading anyway.


Jeremy


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