Re: code optimization in VHDL compilers ?

Srikanth Kamath wrote:
> I'm working on Code optimizer for VHDL.I will be using 3 address code
> as input to my optimizer program .Could you please suggest ways to
> generate 3 address Code from a behavioural description ?
> If you have worked on this /related area, please suggest useful
> material /links
> Thanks


The Allen/Kennedy book has a chapter on HDL code generation:


Optimizing compilers for modern architectures : a dependence-based
approach / Randy Allen, Ken Kennedy


There is some work on VHDL code generation / optimization, look for
work by Peter Wilsey at Univ Cincinatti, and John Willis at CMU from
about 10 years ago.


VHDL Compiler/Simulators are a healthy industry with tens of million
dollars in revenue; so a lot of serious work has happened on
proprietary compilers.


Since VHDL is a simulation language you need to think about the
simulation framework first.


A lot of VHDL specific optimizations have to do with the structure of
VHDL and interaction with a simulation kernel. Perhaps the
optimizations fall into several broad categories:


* data flow/process flow related (how to optimize for process wakeup,
blocking etc. is a general thread in parallel processing work),


* design style/structure related (if a certain kind of digital design,
say a design with edge triggered flip flops, is described in VHDL you
may be able to optimize such code)


* program specialization related (vhdl has a elaboration phase which
looks like program specialization / template expansion)


* parallel execution


* general code optimizations of a process body (should look like
optimizations for a pascal like language; yes, yes VHDL was inspired by
Ada but at this level it is pascal'ish)


There may not necessarily be something VHDL specific to do in the
general code optimizations area; in particular if you are optimizing 3
address codes are you thinking peephole optimization ? at peephole
optimization level are there issues that are special to VHDL ? may be
instruction scheduling of hardware descriptions can have some
interesting wrinkles.


There is a large VHDL test suite that would give you a lot of toy
examples. There is also a repository of university VHDL designs.


You may want to look at the framework Univ. of Cincinatti had for VHDL
as a framework to build your project on.
Google, perhaps Google scholar is your friend :-)

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